fairchij's followup post to scaryracoon about the relationship between the number of transistors and the amount of power you can afford to use without overheating really helped me better understand IR's response to the p-channel question. It also inspired me to read more about the power wall that POET could potentially break down. I found these articles (and one ppt) really helpful in understanding not just the power wall, but the 2 other walls which threaten the continued performance gains in Si CMOS. Furthermore, I think POET addresses all three walls because as the first article explains, we have hit a point where improvements in one area lead to decreases in performace in the other 2 areas. POET would certainly address the power wall, and since it has memory applications it might also impact the memory wall. I honestly dont know about the ILP wall, but maybe the VCSEL would eventually make parallel processing a better option with POET inside:)

Enjoy some weekend reading:

http://www.edn.com/design/systems-design/4368705/The-future-of-computers--Part-1-Multicore-and-the-Memory-Wall

http://www.edn.com/design/systems-design/4368858/Future-of-computers--Part-2-The-Power-Wall

http://www.edn.com/design/systems-design/4368983/Future-of-computing--Part-3-The-ILP-Wall-and-pipelines

http://www.eecs.berkeley.edu/BEARS/presentations/06/Patterson.ppt