Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

Message: New Patent

Found this today:

United States Patent 9,679,987
Taylor June 13, 2017

Fabrication methodology for optoelectronic integrated circuits 


A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) n-type modulation doped quantum well structure (MDQWS) structure with n-type charge sheet, ii) p-type MDQWS, iii) undoped spacer layer formed on the n-type charge sheet, iv) p-type layer(s) formed on the undoped spacer layer, v) p-type etch stop layer formed on the p-type layer(s) of iv), and vi) p-type layers (including p-type ohmic contact layer(s)) formed on the p-type etch stop layer. An etch operation removes the p-type layers of vi) for a gate region of an n-channel HFET with an etchant that automatically stops at the p-type etch stop layer. Another etch operation removes the p-type etch stop layer to form a mesa at the p-type layer(s) of iv) which defines an interface to the gate region of the n-channel HFET, and a gate electrode is formed on such mesa.

It sounds familiar...there's a previously posted patent with the same title, but with a different abstract:

This could be an update 

I haven't read this new one yet, but I think it's either an update or more likely another method.


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