Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Subhash Deshmukh

What we should keep in mind is that mission critical technologies will have strict requirements for redundancy. On the bulk electrical power grid all protection and control is duplicated with separation of communication paths, power supplies, and even separate technologies are used so that a design failure of one will not be duplicated in the redundant protection system.

In phase 2 (year 2)

3.2.1.3 Multi-junction solar cell tiles of different sizes will also be demonstrated using the optimised epi layer.

Another aspect of POET’s technology allows for the integration of a power cell on the same die and we know that Geoff Taylor was able to integrate power management on the cell (which he was pretty excited about) and he regarded it as an important discovery.

We have not even begun to explore all the possibilities of what they are going to be using this technology for.

I mentioned that I felt the scheduled milestones were lined up to match the development needs of POET as we know it.

POETs IR detector:

 Benchmark limits, such as responsivity, on Poet's detector device, far exceed the performance of detectors in the market today. At a bias voltage of 3.3 volts, Poet detectors have demonstrated a room-temperature thyristor-enhanced saturated responsivity of 13 amps/watts at an input optical power threshold of fewer than 200 milliwatts and at an aperture of 10 millimetres. This is about 20 times higher on a three-times-smaller device relative to typical 850-nanometre PiN (P-type, intrinsic and N-type) diodes.

It was disappointing to hear that the IR detector had no disruptive value as a discrete device. I had a hard time understanding this as the sensitivity of the device becomes part of the power equation to the efficiency of the system design. Basically signal strength can be at a lower power output in the transmit circuit.

But what I really felt was important for this detector was the military applications.

So let’s try to get a handle on the development needs for the IR Focal Plane Array.

In one of the earlier patents we find the following:

The GaAs device structures that currently perform the intersubband detector functions are the QWIP (quantum well infrared photodetector) devices. Two significant limitations of the QWIP as currently implemented are the existence of a significant level of dark current that necessitates cooling of the device to 77.degree. K., and the fact that the device is not compatible with GaAs integrated circuits. When originally demonstrated, the QWIP was considered advantageous because of its potential compatibility with GaAs integrated circuits. However, this compatibility has never been established and so present technology combines the GaAs QWIP wafer in a hybrid fashion with a Si read-out integrated circuit. 

It should be noted that the above statement was extracted from a patent dated 2008. The most recent patent applicable to the subject was issued on April 4, 2017 (Imaging cell array integrated circuit) utilizing quantum dot structures.

So in reference to the Read Out Integrated Circuit (ROIC) there is focused effort to get there on the same GaAs die for monolithic integration but it appears from the requirements of the RFP that an exception is allowed.

3.3Phase 3 The third phase of the project will commence with design of ROIC (Read Out Integrated Circuit) for IR imager. Any tuning of the process to achieve the required specifications of the detector array and the onchip integrated ROIC will also be done. As an intermediate step, the detector characteristics may be tuned to achieve target specifications by employing a proven Silicon ROIC with hybrid integration. The design of the readout circuitry for monolithic integration with the detector array will be done in this phase.

(b) Milestone 2 Fabrication of detector array using SCL epi stack process Bump-bonding of Si ROIC 320×256 (or any other mutually acceptable array) Testing and performance evaluation

Again I think the RFP lines up with POETs capabilities and development requirements.

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