Wire Bonding

Wire bonding of the chip. This is the earliest method to connect dies to a package and is still widely used today.

https://youtu.be/V6BA6rSfzjQ

Optical wire bonding approach used by Kaiam.

http://kaiam.com/?page_id=6753

Flip Chip Packaging

Flip chip packaging was introduced in the late 90’s to reduce the size of the package and shorten the interconnect distance. The die is still mounted separately to the package but instead of wire bonds the connection is made through solder bumps. Again efforts to create a like solution with the optical connection using through silicon via’s have been made by many companies.

https://www.youtube.com/watch?v=ZMwiMBdmvSs

Multi-Chip Modules (MCM)

In the early 2000’s higher density packaging utilizing multi-chip modules was required to meet the needs for improved performance and form factor.  Multiple chips were assembled into a single package.

A multi-chip module (MCM) is an electronic package consisting of multiple integrated circuits (ICs) assembled into a single device. An MCM works as a single component and is capable of handling an entire function. The various components of a MCM are mounted on a substrate, and the bare dies of the substrate are connected to the surface via wire bonding, tape bonding or flip-chip bonding. The module can be encapsulated by a plastic molding and is mounted on the printed circuit board. MCMs offer better performance and can reduce the size of a device considerably.

The term hybrid IC is also used to describe an MCM.

Wafer Level Chip Scale Packaging

This is the most advanced packaging system being adopted by the electronics industry today and is being driven primarily by the need for reduced form factor in mobile devices.

https://www.youtube.com/watch?v=CKce_T9ehGM

MCM assembles multiple chips into a package. It is a die scale process.

Wafer level packaging converts the dies into a package.

This process is an extension of the wafer fabrication process, where the device interconnects and protection is accomplished using the traditional fab processes and tools. The “package” is effectively created over the die using wafer level processing techniques.

The major benefit of the Wafer Level Process (WLP) is that all package fabrication and testing is done on wafer. The cost of WLP drops as the wafer size increases and as the die shrinks. With integration, and specifically, by embedding multiple die within the same package and with the use of innovative packaging architectures, form factor can be reduced even further. The technical benefits of WLP are numerous, substantiated, and increasingly difficult to ignore: 1) better reliability performance 2) more functionality and higher levels of integration through multi-chip embedding and complex architectures; 3) form factor reduction via innovative architectures; and 4) absence of substrate. For these reasons, the semiconductor industry will witness the substantial and widespread adoption of WLP technologies in the coming years.

What becomes very apparent is  that POET has found a way to employ it’s Optical  Interposer technology within the most advanced electronics packaging platform creating a best of both worlds approach to optical and electrical integration. A very large number of complete optical modules are created on a single wafer using the economies of silicon packaging creating a disruptive cost structure.

This is a first within the industry. And the sooner this understanding can be recognized by the investment community the faster POET’s share price will begin to reflect this  breakthrough of innovation which is readily scalable and is currently driving advanced development with leading global industry partners who are yet to  be named but likely include Accelink.