As we know a big part of the cost savings associated with the POET optical engine is the ability to test in wafer form.

ITTR has posted some very interesting information in the off topic:

https://agoracom.com/ir/POETTechnologies/forums/off-topic/topics/733590-keysight-formfactor-and-compoundtek/messages/2249132#message

So before we look at the subject tools it is important to review how wafer level photonic testing takes place…what are the access points to transfer light to and from the single mode fiber source of the tester.  

Silicon photonics uses grating couplers which can be placed at convenient locations within the SOI chip but they are very inefficient at capturing light. Silicon photonics requires light and electronics to coexist within the same die so it is important that fiber  can connect at the surface of the wafer (in typical applications) within the real-estate that occupies the photonic waveguides.  

The article that I posted yesterday sums it up in a semi-understandable way:

7.4.1.2 Grating Coupler

A wafer scale testing is not possible with an edge coupler. Therefore, there is a need to develop vertical coupling mechanism… A grating coupler consists of periodic etch structures to diffract the light in a certain direction… the coupling efficiency is very poor for a grating coupler. 

There are three main contributors behind this high coupling loss: diffraction toward the substrate, mode mismatches between the fiber mode and diffracted mode, and second order Bragg diffraction.

POET uses highly efficient spot size converters to couple light at the edge of  the photonic chips so  it would appear to me that in order to perform wafer scale testing grating couplers or similar access points are required to be in place for wafer level testing. No doubt associated with one of many trade secrets.

Let’s take a look at the tool:

https://www.youtube.com/watch?v=izM33rfVVc4&feature=youtu.be

Make sure you read the read thread associated with ITTR post. Suresh is busy man.