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Message: Intel Photonics Engine Promises Energy-Efficient Data Capacity
Not sure if this article was posted/discussed at all yet. It's a month old but I just found and read.
SAN FRANCISCO, April 2, 2020 — A research team at Intel has developed a photonic engine with the equivalent processing power of 16 100-Gb transceivers, or four of the latest 12.8-Tb generation.
At the Optical Networking and Communication Conference in San Diego, Intel researchers described a possible solution to helping computer networks keep up with a growing demand for data.
A 1.6-Tb engine (left) next to an industry standard 100-Gb pluggable transceiver (right). Courtesy of Robert Blum.
Reports from 2019 suggest that approximately 2.5 quintillion bytes of data are produced each day, and that number is growing. All that data has to be routed from consumer hard drives and other processors through multiple servers as it passes through other computers.
According to Robert Blum, director of marketing and business at Intel, the challenge is figuring out how to get data to go in and out of the chip without losing information or slowing down processing. Loss in optical systems still occurs at the inevitable boundaries between materials in a hybrid optoelectronic system.
“To get data to and from the switch ASIC would require 128 pluggable transceiver modules operating at 100 Gb/s or 32 400-Gb transceivers,” Blum said. But, he said, because the distance between the switch and the pluggable modules can be around 12 inches, these electrical links are lossy and power hungry.
“With the 1.6-Tb/s photonic engine, you can co-package the photonics in the same multichip package as the switch ASIC,” Blum said. “To support 12.8 Tb, you would co-package eight of these engines into the same package as the switch ASIC.”
Due to COVID-19, Intel’s live demonstration was held at its San Francisco headquarters instead of San Diego as originally planned, while the team’s paper was presented over video.
Blum said the close integration of the optical components allows Intel’s chip to “break the wall” of the maximum density of pluggable port transceivers on a switch ASIC. More ports on a switch means higher processing power, but a limited number of connectors can fit together before the system overheats.
“With this innovation, higher levels of bit rates are possible because you are no longer limited by electrical data transfer,” Blum said. “Once you get to optical computing, distance is free — 2 meters, 200 meters, it doesn’t matter.”
There’s also the factor of expense. Sending high-speed data over the foot-long copper trays creates a cost barrier while consuming a high amount of energy.
“As speed goes higher, you need more power,” said lead device integration engineer Saeed Fathololoumi. “With optical, it is literally lossless at any speed.”
The co-packaged photonic engine currently exists as a functional demo at Intel’s lab. The demonstration at the conference used a P4-programmable Barefoot Tofino 2 switch ASIC capable of speeds reaching 12.8 Tb/s, in combination with Intel's 1.6-Tb/s silicon photonics engines.
“The optical interface is already the standard industry interface, but in the lab we’re using a switch that can talk to any other switch using optical protocols,” Blum said.
It’s the first step toward an all-optical input-output scheme, which Intel believes may offer future data centers a way to cope with the rapidly expanding data demands of the internet-connected public. For the Intel team, that means working with the rest of the computing industry to define the initial deployments of the new engines.
“We’ve proven out the main technical building blocks, the technical hurdles,” Fathololoumi said. “The risk is low now to develop this into a product.”
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