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Message: Meet The Technical Team - Blue Sands IP

Handal & Associates enjoys a super-specialty in the area of electronics, circuitry and memory intellectual properties. We keep our advantage by maintaining key relationships with experts in the field. In what may be a first, Handal & Associates has entered into a long term, in house relationship with Blue Sands IP for technical support in this area. Blue Sands IP conducts infringement identification; claim charting; prior art analysis and IP valuations. This relationship gives Handal & Associates a clear advantage in litigation and patent licensing negotiations.

The founders of Blue Sands IP have dozens of patents themselves, and have analyzed over 5,000 electronics related patents in their careers. Headed by Alan Sorgi and George Bendak, Blue Sands IP specializes in patent infringement analysis, IP prior art inKevestigations,Patent Litigation support, IP valuation and prosecutions. Together, Alan and George have over 45 years of technology related experience, and have been involved or supervised in the filing, prosecution, and maintenance of over 500 patent applications.

Blue Sands IP

http://www.handal-law.com/meet-the-technical-team.html

George Bendak - [email protected]

PROFESSIONAL EXPERIENCE: Applied Micro Circuits Corp.: AMCC, San Diego. 1999 – 2011

  • Law Department -Solutions Architect and IP Portfolio Manager: 2006-2011 Portfolio Management: Reviewed entire AMCC patent portfolio: Covered microprocessor architecture, SoC design, Network Processors, SerDes, and over 20 other technology areas. Created metrics, technology buckets and rated every patent making it possible to segment them and create mini portfolios for patent sales. Invention gatekeeper evaluated all inventions to determine which to proceed forward with based on contribution to portfolio, marketability and product coverage. Created process for and managed patent life cycle from disclosure to issuance to maintain highest quality and value. Managed and advised outside counsel on office action responses and strategies to keep costs down and to maintain high ratings. Interfaced between inventor and attorneys to maintain breadth of patent as well as focus and faithfulness to original concept. Led initiative to generate patents for ARM V8 processor architecture and SoC design. The first 64-bit hardware implementation. Competitive Analysis: Analyzed, rated and bucketized over 5000 patents from competitors and other companies. Reviewed patents for acquisition potential, infringement possibilities and market directions. Patent sales Created patent clusters and packaged them up for sale with specifically generated marketing materials. Performed product assessments and put together claim charts to reinforce value of patents. Acting CTO for the patent sales. Explained the technologies, concepts, potential infringements and how to determine infringement for the patents. Litigation support Defended company against alleged infringement by analyzing patent claims and showing how products did not infringe Formulated technical arguments to be used by outside counsel
  • Solutions Architect: 2004-2005 Responsible for definition and architecture of next generation 20G-2.5Tbps carrier-class switch fabric with integrated traffic management, customer meetings, interfacing between marketing and engineering, and defining new market opportunities. Responsible for control plane as well as data plane processes, fault tolerance, graceful degradation features and integration with customers' microprocessor complex.
  • Principal Marketing Applications Engineer & Systems Engineer: 2001-2004 Became switch fabric and traffic management expert and responsible for integrating Yuni Networks into the company. Created and managed switch fabric applications group. Responsible for schedules, personnel review, generating collateral, seeking and supporting development partners, system debug, and guiding product to production. Led debug across multiple sites of chip set as well as customer designs.
  • Staff Marketing Applications Engineer & Systems Engineer: 2000-2001 Responsible for specification and system design of AMCC's first OC-192 (10Gbps) Framing and FEC ASSP. This included customer meetings and interfacing with engineering at all steps from specification to manufacturing. Gained experience with SerDes, phase noise, jitter, optical links, serial backplane links, generating documents, collateral, models, field support, generating training materials and teaching classes for FAEs. From this point forward involved in due diligence for mergers & acquisitions. Acquired Yuni Networks switch fabric startup.
  • Sr. Marketing Applications Engineer: 1999-2000 Hired into high-speed (multi GHz) board design group to create IC test boards as well as reference designs. Responsibilities included establishing design processes, design, schematic and board layout, as well as generating feedback to IC design teams. Quickly moved into systems engineering side of marketing.

ComStream Corporation: now Comtech EF Data, San Diego. 1993 -1999

  • Product Line Manager for Satellite Modems & Earth Stations: 1999 Responsibilities include the below as well as planning and specifying future projects, including scheduling and budgeting, product brochures, trade shows and customer support.
  • Staff Engineer/Engr. Group Lead/ Lead Digital, FPGA, and Board designer: 1997-1999 Responsibilities include selecting engineering tools, system design, specifications, Project Engineering/Management, and mentoring junior engineers in FPGA design, digital design, and other design practices. Designed CM601 modem, wrote specifications for Advanced Satellite Modem ASIC's. Created digital specifications and completed digital design of L-band modem project. Supported Broadcast Receiver product line. Designed flexible Viterbi encoder puncturing and constellation mapper, sequential encoders, Doppler buffers, DDS's, and BERT's. Traveled to customer sites to take complaints and trouble shoot.
  • Sr. Engineer: 1995-1997 Redesigned IESS-308/309 Framing Unit which complies with ITU framing and jitter specifications for T1 and E1. Supervised design and development of VHS Modulator. Took project engineer role and completed RF/analog design on High Speed Demodulator including filters, PLL's, improved BER performance and acquisition speed. Designed various IO interfaces.
  • Engineer: 1993-1995 Designed Reed-Solomon codec cards, In-band control channel cards. Responsibilities included schematics, board layout, FPGA design, microcontroller design, interrupt handling, managing firmware development, and written documentation for customers. Tested designs for jitter tolerance and attenuation, performance in degraded channel environments. Designs included DDS's used for frequency locked loops, synchronous and self-synchronizing scramblers, distributed sync word detection, FIFO's, state machines, etc.

Social Science Research Lab (SDSU) Fall 1989 -Spring 1993 Computer technician and Local Area Network consultant/administrator.

Center for Cloud, Chemistry, and Climate Research Jan. 1992 -Nov. 1992 Developed algorithms in C for low bit rate, low loss, variable-rate image compression with application to satellite images.

SDSU Library April 1989 -August 1989 Computer programmer. Implemented program for computer aided instruction.

Computer Skills: Languages: VHDL, FORTRAN, BASIC, C, and 80x86 Assembly. Operating systems: UNIX, DOS, LINUX, Windows, Mac OS. Applications: Office, Orcad, ViewLogic, ACCEL, Synario, FPGA Express, Model Technologies VHDL simulator, Altera tools, Xilinx tools.

Lab Tools: Logic analyzers, oscilloscopes, spectrum analyzers, BER measurement devices, IF noise generators, phase noise and jitter testers, function and frequency generators

Skill Set: Carrier class, high QoS switch fabrics; FEC; Fibre Channel protocol, framing standards, modulation/ demodulation, PLLs, digital design, board design, hardware/firmware/software integration

Continuing Education: Fibre Channel Protocol course Courses in Patent evaluation and monetization.

EDUCATION:

1990-1993 San Diego State University Masters of Science in Electrical and Computer Engineering with emphasis in Communications Theory and DSP. May 1996 Summa Cum Laude

1985-1990 San Diego State University Bachelor of Science in Electrical and Computer Engineering Graduated Dec. 1990 Summa Cum Laude w/ Honors in Electrical Engineering

Publications:

K.S. Thyagarajan, G. Bendak, E.R. Boer, and V. Ramanathan, A Strategy for Satellite Data Archival. Low Noise Variable-rate Vector Quantization with Applications to AVHRR Satellite Images: A Tutorial Review. Signal Processing: Image Communication, Vol. 14, 1999, pp. 245-267

Alan Sorgi, Ken Prentiss, George Bendak, Implementing a 10-Gig Digital Wrapper Structure for Efficient Transport of Heterogeneous Traffic over OC-192. Integrated Communications Design, Light Wave 12/00

Patents:

31 issued and pending patents in the areas of Forward Error Correction (FEC), Framing (Digital Wrapper, SONET, TDM), Switch Fabrics, Power Control and Memory Interfaces in multi-core microprocessor SoC designs.

Alan Sorgi - [email protected]

SUMMARY OF QUALIFICATIONS:

  • Over 20 years of design and leadership experience in a broad spectrum of engineering functions including systems, applications, hardware, software and board design
  • Over 15 years of experience in the semiconductor industry. Skilled at managing products from concept to production release cycle to deliver a high quality manufactured product
  • Over 5 years of managing patent idea generation, patent prosecution and patent monetization efforts, as well as supporting litigation efforts, infringement and non-infringement analysis. Patent technologies evaluated: Processors, Serdes, PLL’s, telecommunications, data communications & storage products, consumer products as well as many others. Evaluated many patent portfolios for acquisition and sale.

AWARDS, ACTIVITIES and ACCOMPLISHMENTS:

  • Profiled in 2010: Licensing Economics Review -The Royalty Rate Journal of IP Profiled in 2008: Best in Class Patent Portfolio Program by Corporate Legal Exchange Chair of AMCC patent committee – Chartered IP Brainstorming Programs
  • 30 U.S. Patents in the area of Telecom, Data Comm., SONET/SDH, FEC, Equalization, and communication links
  • 2010 – Present: Certified Patent Valuation Analyst Board of Advisors Member
  • Represented AMCC on the Center for Wireless Communications Board at UCSD 2001-2004
  • Reviewed research in communication theory, Broadband and Wireless technologies
  • Managed several AMCC university research projects 2001 – 2004
  • Selected to be the Director of Business Process Improvement (BPI) for AMCC
  • Excellence in Scaling Award, April 26,2001
  • Won the Best Marketing Support Award 1998
  • Tech Support Group won the AMCC award for Best in Class -2003
  • Published multiple papers on FEC and SONET/SDH Networking

EDUCATION:

University of California at San Diego (UCSD), San Diego, CA Executive Program for Scientists and Engineers (EPSE), June 2002

San Diego State University, San Diego, CA Masters of Science in Electrical Engineering June 1994 Emphasis in Communication Theory

Loyola Marymount University, Los Angeles, CA Bachelor of Science in Electrical Engineering May 1989

PROFESSIONAL EXPERIENCE

Applied Micro Circuits Corporation (AMCC) -1997 to 2012

Director of IP Portfolio Management 2005 to 2011.

· Directed aspects of IP Portfolio and Managed IP lifecycle. Managed Invention Disclosure Activity. Developed a methodology to measure product coverage gaps. Spearheaded proactive brainstorming sessions. Managed Patent Prosecution Phase. Managed pruning of patent portfolio to achieve quality and expense targets. Measured strength of invention disclosures through the patent prosecution phases. Managed office action responses, appeals and continuation strategy.

· Litigation Support Non-infringement analysis. Non-infringement opinion analysis. Evidence of use research and charts. IP due diligence for sales, acquisitions, and licensing of patents. Prosecution History review and prior art searching.

· Spearheaded and Created an Intellectual Property Monetization Program. Launched an IP Monetization program generating over $30 Million Dollars. Drove results and optimized the value of IP through creativity, vision and leadership. Communicated with executives and chief technologists to understand various business needs and identifying ways to obtain value for IP through patent sales and targeted patent acquisition. Managed the life cycle of patent sales and acquisition projects, including the exercise of efficient project management oversight and budget discipline. Created marketing collateral, technical analysis and valuation assessments for intellectual property. Evaluated business opportunities and delivered transparent, objective analysis. Built relationships with patent brokers and entities interested in the sale and acquisition of patents.

Director of SAN Engineering November 2003 to 2005 Directed all aspects of engineering for a Storage Area Network (SAN) Fibre Channel (FC) Host Bus Adapter (HBA) product:

  • Hardware development (Board Design including FPGA’s and Processors)
  • SW development of Windows/Linux/Solaris/Leadville drivers and applications
  • Improved driver quality by orders of magnitude by developing a root cause methodology
  • Engineering Test (white and black Box testing)
  • Created group 1 month after assuming this leadership role
  • System Interoperability Test for HBA’s within a SAN
  • Technical Support (all levels) for FC Products
  • Drove technical support backlog to a record low in less than 6 months
  • Sustaining and customer Qualification engineering (solved SW and HW issues)
  • Drove backlog of sustaining issues to a 3 year low in less than 6 months

Director of Central Engineering April 2003 to November 2003 Directed all aspects of Central engineering -organization responsible for ASIC tape out to production:

  • ASIC engineering test group
  • Product engineering group (ASIC characterization group)
  • Hardware design group (Evaluation board and characterization boards)
  • Lab automation group
  • ASIC packaging group
  • ASIC design for test (DFT) group
  • Multiple labs (characterization, customer, demo labs) Managed multiple geographically dispersed teams

Director of Applications Engineering October 1999 to April 2003 Grew organization from a few engineers to over 50 in a difficult hiring market. Ran the 1st board level project (optical module development) in the company’s history Created and managed advanced R&D group for innovating channel performance enhancements (FEC, equalization, and modulation schemes for optical systems). Managed 3 dedicated research activities at UCSD through the CALIT^2 program. Managed all PCB design for evaluation, validation, and characterization

  • Founded group responsible for 20GHz substrate and PCB design Managed Product development group
  • Group created over 200 application notes and data sheets for telecom, data comm. products including PLL’s, transceivers, switches, TIA, FEC, SONET/SDH, GBE and FC devices.
  • Responsible for lab services for multiple company groups
  • Staffed state-of-the-art labs with engineers and technicians
  • Built several fully functional multimillion dollar labs
  • Managed Product Support group
  • Developed a world class technical support group from concept to fully supporting over 50 products worldwide in less than 4 months
  • Supported PCI chips as well as SONET/SDH/FC/Ethernet physical layer devices, switches, 2.4G and 10G Transceivers, CDR’s, Framers, performance monitors, PLL’s and FEC chips
  • Developed a method to measure and monitor customer satisfaction and successfully set goals, and drove it higher

Applications Manager April 1999 to October 1999 Implemented documentation standards, templates and metrics to measure performance. Managed 4 engineers

Applications Engineer IV 1998 to 1999 Successfully managed an ASIC design subcontract (2.5 million) from concept to tape out Defined and supported up to 10G SONET/SDH/FC/Ethernet/FEC physical layer devices ATM Forum, IETF, and T1X1 representative for AMCC

Science Applications International Corporation (SAIC) – 1989 to 1997 Manager of Advanced Products Group from 1994 -1997

Center For Mobile Computing Technology (CMCT) Division Managed the first medical product development in SAIC’s history and led the FDA 510k Supervised and directed engineering staff to design, develop, and manufacture high performance embedded and mobile workstations, and flat panel display products Spearheaded all phases (concept, design, development, and manufacturing) of products

Program Manager 1992 -1994 Successfully negotiated and managed fixed price projects and subcontracts Led the development and manufacturing of a rugged 80486 hand-held computer system Proposal manager on over 25 proposal efforts ranging from 200K to 5,000K dollars Managed multiple contract manufactures for board level products

Sr. Electrical Design Engineer 1991-1994 Designed and oversaw 80386, 80486, and PENTIUM embedded applications Developed and utilized various computer interfaces (PCMCIA, GPS, RF LAN/WAN PCMCIA Cards, serial interfaces (RS-232/422, X.25, MIL-STD-1553,IR devices, etc.) Tested products to MIL-STD-461, FCC EMC, MIL-STD-810, and safety (UL) requirements

Electrical Design Engineer 1989 -1991 Designed a XILINX VGA controller interface between an 80386 and a Plasma panel Developed a digital controlled oscillator that controls frequency, amplitude and phase of individual sine waves and combines them to form any complex signal in real time

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