Alliacense is currently focused on licensing and managing the ``Moore Microprocessor Patent™ (MMP) Portfolio.`` The ten fundamental patents in this Portfolio, filed in the 1980s, cover techniques widely used in designing microprocessors, Digital Signal Processors (DSPs), embedded processors and system-on-chip solutions

I. TPL GROUP: EXCLUSIVE MANAGER OF MMP

PORTFOLIO LICENSING PROGRAM

The TPL Group has exclusive control over all Licensing and Litigation with respect to the MMP Portfolio.

II. INDUSTRY-LEADING LICENSEES

Unlike many disputed or questionable patents, it has been widely acknowledged that the MMP Portfolio contains several fundamental building blocks of modern microprocessor architecture and implementation. As a testament to this practical reality, and in response to their requests to be first, industry leaders Intel and AMD each recently purchased MMP Portfolio licenses to cover their products, and to protect their corporate treasuries from massive exposure. Going forward, the MMP Portfolio Licensing Program will reward first movers in their industry sectors with dramatic discounts. By design, this structure enables nimble and forward-thinking companies to disadvantage their competitors.

III. SCOPE OF THE MMP PORTFOLIO

Running through year of 2015, the MMP Portfolio consists of: US 5,440,749; US 5,530,890; US 5,604,915; US 5,659,703; US 5,784,584; US 5,809,336; US 6,598,148; European Counterparts and Japanese Counterparts. The most widely recognized patents in the portfolio are:

US`336: Clocking CPU and I/O Separately. The MMP Portfolio is NOT limited to ``high speed`` microprocessors. In fact, during the past year of intense study of hundreds of various microprocessor designs, no correlation at all has been found between the speed of a microprocessor and the application of US`336. Use of US`336 is prevalent across most microprocessors from low speed microcontrollers to sophisticated systems on chips. Advertised advantages include: cost reduction, instant-on execution, failsafe operation, EMI reduction, and power savings. It is a modern requirement from a design for test (``DFT``) perspective.

US`584: Multiple Instruction Fetch. Multiple Instruction Fetch architectures are the norm in environments where limiting power consumption is critical; e.g. portable products. Various techniques can be employed to achieve the Multiple Instruction Fetch, and marketing terminology includes ``VLIW,`` ``SIMD,`` ``MIMD``, ``Superscalar,`` etc.

US`148: On-Chip Oscillator and Embedded Memory. Shares the on-chip oscillator feature with US`336, in addition to memory covering more than majority of chip. Also includes claims pertaining to multiple CPU, array or cell implementations. The vast majority of the system on chip (``SoC``) products are affected.

Virtually every product manufactured today utilizing microprocessors or embedded processors will require an MMP Portfolio license. The Portfolio covers microprocessors and the Systems containing microprocessors.

IV. PORTFOLIO BACKGROUND

The TPL Group assisted Charles H. Moore in the development of the MMP Technology and Patents beginning 1989. Mr. Moore, also the inventor of the Forth computing language, now serves as Chief Technology Officer of the TPL Group.

Managing intellectual property partnerships worldwide

Alliacense is a TPL Group Enterprise

Founded in 1988, the TPL Group has emerged as a world class intellectual property management company. Alliacense represents TPL`s cadre of senior executives currently focused on managing the Moore Microprocessor Patent Portfolio.

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