Don't worry about the size of a GaAs chip compared with its Si counterpart. GaAs performs much faster than Si at equivalent feature sizes.

Here's a Geoff Taylor quote from the PCWorld article:

http://www.pcworld.com/article/2033671/breaking-moores-law-how-chipmakers-are-pushing-pcs-to-blistering-new-levels.html

"OPEL only recently exited the R&D stage and hasn't tried to make itty-bitty transistors at Ivy Bridge's 20nm size, but the company claims that at 800nm, gallium arsenide processors are faster than today's silicon and use roughly half as much voltage.

"If you wanted to match the speed of today's silicon processors, at roughly a 3GHz clock rate, you wouldn't have to go all the way down to 20 or 30 nanometers," says OPEL chief scientist Dr. Geoffrey Taylor. "Heck, you could probably hit that at 200nm." And that's using planar technology, not 3D transistors."

I'm still working through the article TechGC posted, there's a few concepts I figure out before I can gauge how difficult it will be to scale down POET to 100nm. I also have to get my head around the p- and n- channel clock frequencies to figure out which one determines the overall performance. I'm assuming that the p-channel improvement is the most important since the n-channel is already far beyond CMOS.

Here's where we were reported to be most recently in the RF Milestone NR:

http://www.poet-technologies.com/wp-content/uploads/2013/03/NR-4Mar2013-POET-Milestone4.pdf

"Specifically for this milestone, 3-inch POET wafers fabricated at BAE Systems (Nashua, NH) yielded submicron n-channel and micron-sized p-channel transistors operating at frequencies of 42 GHz and 3 GHz respectively. These operating frequencies are expected to be improved even further in the short term to up to 300-350 GHz range for the n-channel device."

The quote above says "submicron", so it can be assumed they are working on the smaller feature sizes (maybe 700nm?), and the speed improved over the previously reported n-channel frequencies of 38GHz from the laser NR:

http://www.poet-technologies.com/wp-content/uploads/2012/12/NR-04Dec2012-ModifiedLaser.pdf

"Going forward, technology development will lower the threshold current, increase the output power and optimize the in-plane version of the VCL. In addition, the complementary transistor circuit capability will be enhanced by reducing the feature size to the 100-nm scale incorporating ODIS' new self-aligned contact technology. With transistor cutoff frequencies around 38-GHz for a 0.7-um gate, the scaling is expected to produce 260-GHz transistors with commensurate improvements in circuit speed."

So here we are working in the sub micron range also, but they don't report the p-channel frequency. Oddly, the latest MS achievement was completed with larger gates (1um) which I'm guessing was done because they had to quickly switch to MS6 at the request of the SSC:

http://www.poet-technologies.com/wp-content/uploads/2013/06/NR-27June2013-MilestoneCompInverter2.pdf

"The OPEL lab demonstrated both nHFETs and pHFETs, with symmetrical positive thresholds, as an integrated circuit with thresholds of +/- 0.5V and VD=2V for 1um gates. Going forward, logic circuits will be integrated with in-plane lasers and detectors with the goal of reducing linewidths towards CMOS state-of-art circuits."

I believe they will continue to shrink these concurrently as they work toward (new) MS8.

Finally (I know this post is getting long!) here's the challenge we face in shrinking POET to 0.1um according to the author of the article TechGC posted, where p-channel transistors relate to "holes" (lacking electrons). I'm going to continue to look into the p-channel for GaAs because it may be the thing that makes the difference between POET HEMTs and others that have failed in the past (aside from the "look and feel of CMOS mentioned below).

http://www.compoundsemiconductor.net/csc/features-details/19732104/Is-nanometer-scale-III-V-CMOS-cool-enough-to-rejuvenate-Moore%E2%80%99s-Law.html

Dealing with the holes

Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon. Mobilities in silicon have improved through the addition of strain in the material, with the performance of the pchannel now approaching that of its n-type cousin. It will be interesting to see if the same trick will work for the arsenides.

Other options for the p-channel are also available. Measurements have revealed antimonides mobilities in the 1500 cm2/V.s range and p-channel transistors have already been fabricated. Germanium transistors are also of interest. Germanium has a high hole mobility that is enhanced through strain. It also has the advantage of being nearly lattice-matched to GaAs. This suggests a possible CMOS platform in which germanium and III-V transistors are integrated side by side.

Last but by no means least on the list of major challenges is the need for a future III-V CMOS technology to closely “look and feel” like the silicon incumbent. Meet this goal and III-V CMOS can then exploit the tremendous economy of scale in the silicon industry. The most likely incorporation of III-Vs in the CMOS road map is via an enhancement to the existing technology through the insertion of a III-V channel - much like the recent additions of high-K/metal gates or strain. Exactly how this plays out will be influenced by what emerges as the best option for the p-channel device, and it is possible that the future will witness two different channel materials sitting side by side, on top of a silicon wafer.

With III-Vs knocking on the door of the CMOS roadmap, it’s clear that the present generation of III-V scientists and engineers have an opportunity ahead of them to shape the future of mainstream electronics. Has there ever been a better time to be a III-V semiconductor technologist?