Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: ieee article

That's an excellent article, rob!

Looking at the graph below, I recalled that I saw a relevant youtube video that shows some of the sleight of hand the big boys are using when they try to shrink to the next node...

https://www.youtube.com/watch?v=jz4VMvDY-W8

As you can see, the yellow line (gate length) hasn't really been reduced significanly alongside the other two. Look at the orange line! They failed to shrink the half pitch this year. I guess this is what was meant in some of the articles I read where the transistor was going to 14nm, but on a 20nm process. More space between features I guess, but no additional transistors compared with the previous node.

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