Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: IP Challenges at advanced nodes (silicon)

Good find, disco68! I like especially this statement:

According to Yee, at 90, 65/55 and 40nm, a lot of foundry enablement was in existence. "At that point, you could choose a foundry and it didn’t have a big impact on you. …"

Okay, the article is not really about the larger node sizes but instead about the smaller ones – and the difficulties associated with them. Seems 40 nm was a carefully and cleverly chosen target, because …

  • it avoids the difficulties of the smaller nodes sizes – they can be tackled later
  • it maximizes the number of foundries which can make use of the POET technology with their existing mainstream equipment, and thus the foundries' hurdle to shell out money for licensing the technology will be low,
  • it maximizes the customers' freedom to select their foundry of choice, thus maximizes the number of potential customers, and thus maximizes POET's revenue.
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