Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Dear Agoracom Family,

I want to thank all of you for your patience with us over the past 48 hours and apologize for what was admittedly a botched launch of our new site.

As you can see, we have reverted back to the previous version of the site while we address multiple forum functionality flaws that inexplicably made their way into the launch.

To this end:

1.We have identified 8 fundamental but easily fixable flaws that will be corrected in the coming week, so that you can continue to use the forums exactly as you've been accustomed to.

2.Additionally we will also be implementing a couple of design improvements to "tighten up" the look and feel of the forums.

Have a great Sunday, especially those of you like me that are celebrating Orthodox Easter ... As well as those of you who are also like me and mourning another Maple Leafs Game 7 exit ... Ugggh!

Sincerely,

George et al

Message: Re: Accelink Patent for 400G Optical Transceiver

Fortunately the patent does not provide any detailed description of the modules and if it did that would be a little scary as there is no technology transfer of the optical interposer with Accelink. What it does demonstrate is the motivation for Accelink to build transceivers using the POET interposer platform optical engines.

The original application date of the patent precedes the POET optical interposer. It is  not difficult to recognize that Accelink needed a platform that could achieve a means to produce this generation/configuration of 400G transceiver economically utilizing PAM4 with up to eight 25G directly modulated lasers or four 50G directly modulated lasers.

I have stated in the past that the POET optical interposer platform will drive new standards as it would be expected to change the economics of each configuration. Optical connections become low cost with added performance benefits associated with architecture including thermal control. Thus a much greater number of connections can be tolerated to allow efficiencies/costs of each active device and even the type of active device to play a greater role in the economics of the products. So high speed assembly, low insertion and waveguide loss combined with a significantly reduced bill of goods. A low stress low temperature process which enables migration to 12 inch silicon size will allow a continued reduction to cost, throughput and enable new generations of application and design.

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