I’d like to draw attention to the post by godotiscoming in the off topic forum (22Feb, Re: Hybrid integrated photonics cultivate a value chain).

https://agoracom.com/ir/POETTechnologies/forums/off-topic/topics/737412-hybrid-integrated-photonics-cultivate-a-value-chain/messages/2259208#message

In particular there is a link to a November 2019 presentation by Juniper Networks on Silicon Photonics.

https://www.juniper.net/assets/us/en/local/pdf/nxtwork/silicon-photonics.pdf

As I read the slides from Juniper, the similarities with the themes presented by our Poet executives was quite striking to me.

For example, some points I find interesting regarding these slides:

Slide 4 on Technology Comparison refers to Silicon Photonics 2.0, and the “holy grail” where the laser is integrated into the silicon die.  They believe only 2 companies  can currently do this.... So are we one of the two? Or possibly our product helps make Juniper one of the two?

Slide 7 on key integration characteristics:

Mature silicon photonics passives

Integration of multiple III-V materials

Active materials defined by lithography

No critical alignment

Hermetic at Chip Scale

Wafer scale processing

These highlights all sound very familiar

Slide 8 highlights some products - 400G-FR4 and 400G-DR4 full Transmit (Tx) and Receive (Rx) functionality in a silicon die, mainstream fab manufacturing, fully integrated transceiver, standard testing methods. 

I note that the products we are focusing on for our first deliverables for the Datacenter 400G market are 400G-FR4 and 400G-DR4 as well - reference slides 13 and 25 from our September 2019 AGM presentation. 

https://poet-technologies.com/docs/agm2019/AGM%20Meeting%20Presentation_FINAL_Web.pdf

Slide 12 Integrated Troubleshooting 

Incorporates an Integrated Optical Loopback Switch Between TX and RX - allows Optical verification during manufacturing and in-service diagnostics

We also incorporate a loop back feature in our design - reference the link to the approved patent that Stubbel01 posted in November.

https://agoracom.com/ir/POETTechnologies/forums/discussion/topics/734161-patent-method-of-forming-an-hermetic-seal-on-electronic-and-optoelectronic-packages/messages/2250860#message

I know that the examples cited in the patent positioned the “loop back” testing feature in a sacrificial part of the wafer but in some designs it could also be retained as part of the device to aid with future in-service troubleshooting?

Slide 13 - leverages existing silicon Supply Chain model - same as Poet’s approach - see Sept 2019 AGM slide 15 - Fab-light Model

I know a little knowledge is dangerous so this may be way off track, but at the very least I believe it reinforces that our solution is ticking off most of the boxes that the industry players are looking for.

IMO,

killer66