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We are POET Technologies. Our vision for the company is to become the global leader in chip-scale integrated photonics solutions by deploying our Optical Interposer technology, enabling seamless integration of electronics and photonics for a broad range of vertical market applications for a smarter, more connected world.
We hire the most innovative talent in the world to solve the industry’s toughest problems in opto-electronic integration, providing our customers with significant advantages in performance, energy savings, cost, design simplicity and flexibility. POET Technologies’ Optical Interposer platform creates solutions for customers in diverse markets including Data Centers, Telecom, Internet of Things, (IoT), Artificial Intelligence and Machine Learning, as well as Automotive Sensing.
POET Technologies has developed an optical integration platform that provides industry with a low cost high performance solution for data communications to meet the growing demands of the digital world.
To begin to understand what it is that POET has developed and how they came up with this solution we need to look at the inventor of the platform and his background. Dr. Suresh Venkatesan joined POET Technologies from GLOBALFOUNDRIES where he was the Senior Vice President, Technology Development. He was appointed by Ajit Manocha who is now the president and CEO of SEMI. SEMI is the global industry association serving the electronics manufacturing and design supply chain. Ajit Manocha was formerly CEO at GLOBALFOUNDRIES.
With a very comprehensive understanding of the leading edge of semiconductor development Suresh has looked at what is and isn’t possible. He has investigated a number of optical integration technologies and the POET Optical Interposer Platform is an extension of some of the most leading edge semiconductor processes. Wafer-level packaging is an advanced process for packaging ICs directly onto a semiconductor wafer.
The continued shrinking of form factor for mobile devices in particular drove the need for significantly more innovation. Instead of first assembling the chip into a package – a process done individually at die scale – the path was to “convert the chip into a package”.
Newer, more advanced products, such as BGA packages and flip-chips, have become more complex and go beyond wire bonding to get signals onto the die. Today’s portable electronics and mobile devices can only afford enough board space to use the smallest components.
One of the major benefits of wafer level packaging (WLP) is that all package fabrication and testing is done on the wafer. The cost of WLP drops as the wafer size increases and as the die shrinks. With integration, and specifically, by embedding multiple die within the same package and with the use of innovative packaging architectures, form factor can be reduced even further. The technical benefits of WLP are substantial and provides the foundation for heterogeneous integration. Higher levels of integration through multi-chip embedding. It allows industry to take the best material sets for each chip function, optimise them separately and then connect them together in a manner that provides superior signal integrity.
What Suresh has created is an extension of this leading edge process for electronics by adding an optical layer at the surface of the electrical interposer. He has created an optical interposer that adds a parallel optical laneway that provides a level of optical connectivity that has never been achieved before in a CMOS fabrication flow. The results have been industry leading in terms of coupling efficiencies and because this is done in an automated fabrication flow without human requirements to manually align the optical connections it is the lowest cost solution available to meet industries growing needs to replace electrical transmission of data with photonics.
POET has recently received coverage in important industry publications. I have added market cap to the companies listed.
In the context of China-US trade war and COVID-19 epidemic, it will have a big influence on this market. Photonic Integrated Circuit Report by Material, Application, and Geography – Global Forecast to 2023 is a professional and comprehensive research report on the world’s major regional market conditions, focusing on the main regions (North America, Europe and Asia-Pacific) and the main countries (United States, Germany, United Kingdom, Japan, South Korea and China).
The report firstly introduced the Photonic Integrated Circuit basics: definitions, classifications, applications and market overview; product specifications; manufacturing processes; cost structures, raw materials and so on. Then it analyzed the world’s main region market conditions, including the product price, profit, capacity, production, supply, demand and market growth rate and forecast etc. In the end, the report introduced new project SWOT analysis, investment feasibility analysis, and investment return analysis.
The major players profiled in this report include:
Market cap included (Dec 8), (Jan 3)
NeoPhotonics Corporation….($450 Million), ($456 Million)
POET Technologies Inc……($150 Million), ($238 Million)
II-VI Incorporated………….. ($7.5 Billion), ($7.9 Billion)
Infinera Corporation…………($1.73 Billion), ($2 Billion)
Intel Corporation……………..($206 Billion), ($204 Billion)
Price: Single User License: US$ 2850 Multi User License: US$ 5800
To demonstrate the importance of the Optical Interposer Platform let’s look at one of the numerous solutions this platform offers industry.
October 14, 2020 OIF Webinar - "Co-Packaged Optics - Why, What and How”
Representing Intel is Richard Jones, Senior Principal Engineer. He leads the laser development team at Intel’s Silicon Photonics Product Division.
One of the key attributes that you need to connect your laser to silicon photonics die is to look at coupling loss. This is one of the challenges around the remote lasers. For integrated lasers at Intel we measure about .5dB coupling loss between the laser and the silicon photonic waveguide. For remote lasers we are estimating coupling loss to an optical fiber to be about 2dB with a similar coupling loss between the fiber and the silicon photonic chip. You can tweak these numbers if you can improve the coupling there but you are about 4dB coupling loss for remote lasers which needs to be accounted for and minimized where possible.
So why would you actually do this? It has been mentioned before but thermal environment. So switches are getting hotter as the bandwidth increases independent of your choice of optics whether it is pluggable or co-packaged. The addition of Co-Packaged Optics drives different thermal decisions particularly around the thermal cross talk between the electrical and photonic chips.
Our internal assessment at Intel is that both fan cooled and liquid cooled are possible for next generation switches and that is applicable to ether CPO with integrated lasers or remote lasers.
The performance of lasers varies over temperature.
The lower temperature of the remote laser (Slide 7). The graph on the right shows measured laser bias required to emit different output power for different temperatures. The grey bar shows estimated temperatures for remote and integrated lasers. So as you can see remote lasers can work at lower temperatures but the lower temperature does not compensate for the additional 4dB of loss as demonstrated by the circles on the graph.
Operating the lasers at lower temperature does not compensate for the additional 4dB of loss as demonstrated by the circles on the graph. So it is really key for remote lasers to reduce that coupling loss. Although operating the lasers at lower temperature does allow them to emit higher output powers.
For integrated lasers the real question is how hot the environment they are working under is. Pushing the laser at temperatures above 100’C will be challenging.
So looking at some of the laser reliability here I am assuming that the mature manufacturing process has been used weeding out premature failure with burn-in. So the focus will be on the random failures that occur during the operating life known as failure in time or FIT rate.
Refer to slide 8 and particularly to slide 9.
Field serviceability allows relaxation of acceptable failure rate.
If the laser fails then the entire switch package needs to be replaced unless redundancy has been added.
Now let’s look at a recent news release by POET Technologies. As noted in the Intel presentation coupling loss of the remote laser is estimated at 4dB. POET’s coupling loss of their remote laser solution is identified at less than 1dB.
December 8th, 2020
– POET Technologies Inc. (“POET” or the “Company”) (TSX Venture: PTK; OTCQX: POETF) the designer and developer of the POET Optical Interposer™ and Photonic Integrated Circuits (PICs) for the data center and tele-communication markets, announced today that it has completed and tested its designs for a line of high-performance remote laser light source products for 400G FR4, 800G and Co-Packaged Optics (CPO) applications in Cloud Data Centers, named
For makers of conventional and Silicon Photonics-based optical transceivers, the product line offers a fully aligned, tested, and multiplexed laser light source attached to an output fiber, eliminating the difficult and costly step of four laser alignments in optical transceivers. For makers of next generation network switches that require the combination of switch components and optical components in a single package, commonly referred to as “Co-Packaged Optics” (CPO), using products will reduce heat generation within the package, which is a common cause of component failure. When used as a remote laser source, POET’s is expected to improve overall system reliability for both transceiver and CPO applications by offering the ability to replace failed laser assemblies in the field, without disturbing other components and sub-assemblies. Laser failures have proven to be the cause of a large majority of sub-assembly failures in both optical transceivers and co-packaged optics applications.
products are configured as a Transmit Optical Sub-Assembly (TOSA) incorporating four Continuous Wave (CW) lasers into the waveguide matrix of POET’s proprietary Optical Interposer, meeting the CWDM4 and FR4 technical specifications. The 400G version is upgradeable to 800G with the incorporation of additional components. The is completely customizable and can support a wide range of output power from 15mW to 60mW depending on the application. In all cases, incorporates POET’s proprietary designs and assembly features that deliver an industry-leading laser coupling efficiency of >80% (power loss = <1.0dB), while maintaining wafer-scale integration capability. These results are significantly better than the best results observed with competing integrated approaches. Better coupling efficiency allows the use of lower power, more reliable lasers to achieve the same output. POET will begin sampling the product line to customers beginning in Q1 2021. Following qualification with customers, the Company expects to begin volume production in Q4 of 2021.
According to LightCounting, the market for 400G optical transceivers in all formats will grow to over $3 billion by 2025 from an estimated $0.5 billion in 2021. The market for optical connectivity, also known as chiplets in co-packaged optics, is forecast to be more than $4 billion in 2028.
POET Technologies management goes “Beyond The Press Release” to discuss today’s news. Investors and other interested parties are encouraged to visit the following link the evening of Tuesday, December 8, 2020 to view the interview:
Since that news release POET has announced an additional industry first.
December 17th, 2020
– POET Technologies Inc. (“POET” or the “Company”) (TSX Venture: PTK; OTCQX: POETF) the designer and developer of the POET Optical Interposer™ and Photonic Integrated Circuits (PICs) for the data center and tele-communication markets, announced today that it has completed and tested its high-speed Directly Modulated Laser (DML) designs using a distributed feedback (DFB) structure and successfully “flip-chipped” these lasers onto the Company’s Optical Interposer platform, which also incorporates several other industry-first accomplishments.
The flip-chip assembly technique enables a true single-chip, fully integrated Optical Engine to be produced at wafer-scale, resulting in the lowest-cost, smallest-size 100G CWDM4 Optical Engine with a form factor of 9mm x 6mm, while including banks of four lasers, four monitor photodiodes, four high speed photodiodes, a multiplexer, demultiplexer, taps for power monitoring and features supporting a self-aligned fiber attach unit.
“Without being able to flip-chip the lasers, we would be unable to assemble Optical Engines at wafer-scale, which is the single most important driver of cost. Wafer-scale processing enables the production of high unit volumes at low incremental costs, ultimately allowing us to reduce the cost of building photonics devices by 25% to 40% compared to conventional approaches,” stated Suresh Venkatesan, Chairman and CEO of POET. “Following our successful demonstration of this flip-chip assembly process, POET can now readily incorporate these lasers and other active devices into derivative optical engine configurations, supporting data communications applications such as 200G CWDM4, 100G CWDM6, and 100G LR4, telecom applications such as 5G, as well as other applications that could benefit from the small size and low cost of our platform technology.”
Four DML lasers are commonly used in 100G transceiver applications, a key initial target market for POET’s Optical Interposer, enabling high speed optical communication in the 2 to 10 km range. Operating at speeds of 25 gigabits per second (GPS), POET’s family of four DML lasers of different wavelengths are the first known commercial 25G DFB-type DML lasers to utilize a flip-chip process to passively align and bond to electronic and optical circuitry on the interposer platform, while maintaining optimal performance. Given the estimated total available market (TAM) for 100G transceivers of approximately $2.5 billion, POET believes that its recently formed JV company, SuperPhotonics Xiamen, can achieve annual revenue of over $100 million within this single market segment in the 2024-25 time frame.
Flip-chip assembly of electronic devices on circuit boards, MEMS (Microelectromechanical Systems) and other devices is an advanced manufacturing process for achieving electrical interconnect (often referred to as 2-D, 2.5-D and 3-D) in semiconductor architectures. To achieve the benefits of the planar architecture of POET’s Optical Interposer that facilitates wafer-scale processing, flip-chipping of lasers was an important development milestone, requiring POET to demonstrate that it could simultaneously optimize the RF (radio frequency) performance of the flip-chipped DML laser on interposer while preserving a low RIN (relative intensity noise) measurement both before and after assembly. RF performance relates to the quality and power of the electrical signals, while RIN is a measure of stability of the lasers that are assembled on the Interposer.
POET Technologies goes “Beyond The Press Release” to discuss today’s news. Shareholders and other interested parties are encouraged to check back on this link before market open on the morning of Tuesday December 22, 2020.
Notable comments from Ron Stone technical source manager at Facebook.
Operating Implications at Scale (slide 5)
Challenges for CPO vs Front Panel Pluggables
When we are thinking about Co-Packaged Optics clearly this is a new challenge that we need to embrace which is Co-Packaged Optics by definition are not serviceable.
So people have considered things like using external lasers or spare channels if the lasers are integrated into the co-package as possible options to mitigate failure modes.
Also in terms of reliability it is important for us to consider security of supply ecosystem of CPO. For this to be deployable at scale of supply chain redundancy. So that kind of implies as Mark (Cisco) was mentioning standardized interfaces….
He then goes on to talk about power and the need to maintain the existing network power footprint to allow for infrastructure reuse thus the need for Co-Packaged Optics.
So in nutshell what POET has achieved precisely aligns with what Facebooks needs are.
Using external lasers is the solution to isolate the heat and control the heat that they produce to avoid premature aging and failure of the laser. But if this laser does fail it is swapped out. The lasers must have best in class coupling efficiency or the power budget cannot be met.
This is a circular argument that leads directly to POET.
Recall a past post where Facebook talked about the incidence of laser failures associated with 100G pluggables described as Dead On Arrival: reference https://agoracom.com/ir/POETTechnologies/forums/discussion/topics/748919-angeltech-virtual-live-i-pic-international-breakout/messages/2287630#message